Integrated circuit layout software tools for placing and routing (“PAR tools”) are well known. Such PAR tools may use static timing analysis to guide a layout process to meet user-specified timing constraints. For example, a user may request that a particular “circuit path” within an integrated circuit have a delay which is less than some specified value. By “circuit path” it is meant an ordered list of logic and interconnect resources, without any repetition of any of such resources. A circuit path starts from a “path source,” namely, the first or origination resource of the circuit path, and ends at a “path sink,” namely, the last or destination resource of the circuit path.
A static timing analyzer might use logic and interconnect delays along such a circuit path to determine if the total delay along the path is less than the specified value. However, checking each individual path is impractical given the number of individual paths in a conventional complex integrated circuit.
Consequently, block-oriented static timing analysis may be used to find a worst case delay of all paths for a logic block. The worst case delay value is then compared against a specified value. Additionally, worst case “Absolute Slack” of any interconnect resource for all paths passing through such resource may be determined with block-oriented static timing analysis. By “Absolute Slack” it is meant as the difference between a specified time of arrival of a signal to a location and the actual time of arrival of the signal to the location. Notably, for purposes of clarity, Absolute Slack is described in terms of maximum delay requirements as specified by a user. However, absolute slack may be used for minimum delay requirements, or delay requirements between maxima and minima delay requirements, as specified by a user.
However, for clocked circuits, conventional absolute slack computation fails to take into account phase differences of a clock signal relative to path source and sink, and thus may result in a sub-optimal optimization of design clock frequency for an integrated circuit.
Accordingly, it would be both desirable and useful to provide means for accounting for differences of a clock signal relative to path source and sink for placement or routing of an integrated circuit.